Accelerate package thermal modeling in electronics cooling design

On-Demand Webinar

Learn about faster generation of semiconductor package thermal models

This webinar focuses on thermal modeling of electronics packages to predict the component temperature in system-level electronics cooling simulations during development. From semiconductor device OEMs supporting the electronics supply chain to engineers selecting and integrating components into electronics products, it is important to have appropriate accuracy and simulation speed to suit the design stage and an efficient means to generate thermal models with available information.

The webinar briefly reviews different modeling levels for evaluating junction temperature and heat dissipation in common discrete components to more complex packages. The short review covers JEDEC standards and the range of simple models, 2-resistor (2R), multi-resistor network (incl. DELPHI Compact Thermal Models) through to detailed component thermal models.

The major part of the presentation illustrates an accelerated workflow to create detailed package thermal models of different types and integrate them onto a PCB of a system-level electronics example model, considering the mounting and copper trace level details (EDA data). The Simcenter Flotherm Package Creator application, within CAD-centric Simcenter Flotherm XT electronics cooling software, is used to show how to generate package models faster than typical approaches. Additionally, an overview is included in achieving the highest accuracy using thermal transient measurement data to automatically calibrate models.

Topics include:

  • Appropriate package thermal modeling in 3D CFD electronics cooling simulation vs design stage
  • Creating detailed package thermal models – considering internal elements (die, substrate, wire-bond, encapsulate, etc.) alongside how to define geometric, thermal properties and modeling specification
  • Related areas: modeling package types (e.g QFN, MQFP, TO-220), Ball Grid Arrays (BGA), Fan-out Wafer Level Packaging (FOWLP), local PCB trace modeling under components, and more

Register Now

Leave a Reply

Your email address will not be published. Required fields are marked *

Fill out this field
Fill out this field
Please enter a valid email address.