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On-Demand Webinar

Presenter: Gowrav Ravindra

Cost & Risk Impact of Late Fault Detection in PCB Systems Design

Brief Summary of Webinar:

Background:
Increasing performance requirements coupled with a pressure to improve product quality are driving engineering teams to consider alternatives to their current validation approach. Best-practice design processes validate the digital twin (a model of your design) early and often to minimize re-spins and shorten the overall design cycle. This ‘left shift’ approach enables design engineers and layout designers to validate within their native environment, minimizing the bottleneck waiting for specialist reviews, and freeing the specialists to resolve the remaining critical issues. This presentation will look at new, integrated technologies for analysis and verification deployed throughout the design process, including schematic verification, signal & power integrity, electrical sign-off, thermal, vibration and manufacturability.

Who Should Attend:

  • Electrical Engineers
  • PCB Designers
  • Project Managers

Post the webinar, the participants will be able to:

  • Get exposure to Design Verification
  • Understand the importance of Validations
  • Minimize the bottleneck waiting for specialist reviews

REGISTER NOW


Presenter - Gowrav Ravindra

Gowrav has total of 10+ years of expertise handling PCB for High Power & High Voltage designs and High-Speed Design. Involved in layout design for applications in the area of Power Electronics, Custom Power Supplies, Analog Circuits, Digital Power, Solar and Renewable Energy, High-Speed Design differential pair min/max length matching – like DDR 2/3 boards. handling the portfolio of Mentor PCB software’s Pre-Sales & post Sales.

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