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C++/SystemC Synthesis

Catapult is the premier ASIC and FPGA HLS solution. With C++ and SystemC support, designers may work in their preferred language, increasing efficiency and quality. With 80% less code and 1,000x quicker simulation rates than Verilog. The advantage you require is HLS design and verification.

Key Features

Blazing Fast Design, Verification & Implementation

HLS is more than simply RTL in C++/SystemC. Catapult provides “correct first time” RTL for ASIC and FPGA design, verification, and implementation. With Design Checking, you may avoid surprises, enhance coverage with Catapult Coverage, and close timing on the most recent nodes with a multi-VT Physically aware flow.

Language Freedom

Native Dual-Language Support of SystemC and C++


C++ or SystemC are options that allow teams to choose the most effective technique for their design work. Catapult has you covered, whether it’s the better simulation and verification performance of sequential C++ with the AC data types (hlslibs.org) or explicit concurrent modelling with SystemC and MatchLib (also utilising the AC types).

Catapult Design Checker

Advanced Design Checking

Catapult Design Checker Finds Bugs Before Synthesis


Find code problems you didn’t even know you had! Catapult finds poor logic-creating uninitialized variables, array bounds violations, and other code errors that might emerge in C++ or SystemC without the need of a testbench and by combining lint and formal engine analysis. Before synthesis, Catapult even gives comments on anticipated HLS QoR issues.

Coverage Driven Verification

Catapult Coverage Accelerates Verification Before RTL


Traditional RTL metrics like statement, branch, expression, and toggle coverage should be used. Combine with SystemVerilog functional verification methodologies to get high quality HLS-aware coverage without sluggish and expensive RTL simulation. Faster C++/SystemC simulation speeds up your verification efforts and “first time correct” RTL delivery.

Catapult Coverage Accelerates

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