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High-Level Synthesis Tools

Catapult provides cutting-edge HLS tools for FPGA, eFPGA, and ASIC with industry-leading C++ and SystemC support. With solutions for great Quality Results through physical awareness, low-power estimation-optimization, design checking, lint, formal, and code coverage, Catapult will hasten your success.

Catapult High-Level Synthesis Solutions

Siemens’ Catapult Synthesis systems offer support for the C++ and SystemC programming languages, FPGA and ASIC independence, ASIC power estimation and optimization, and the most recent advances in physically aware multi-VT area and performance optimization.

C++/SystemC Synthesis

A complete HLS tool that meets all of your requirements for the trickiest ASIC and FPGA designs.

Low Power Solutions

When it comes to early architecture power estimation, plus optimizing for low-power ASIC RTL, Catapult has what you need.

Physically Aware HLS

Catapult maintains up with shrinking geometries with design adaptability, tangible downstream data, and outstanding QoR.


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