How can you achieve outstanding quality of outcomes at a reasonable runtime? A new place-and-route paradigm is necessary to address the difficulties of design execution at advanced process nodes.

Challenges in Digital Place-and-Route

Modern SoC design has numerous difficulties, including balancing design complexity, performance/power/area targets, and time-to-market. Design rule complexity and meeting timing make design closure more difficult than ever, necessitating a paradigm shift in place-and-route.

Achieving DRC Closure

The extensive usage of mixed-height cells, EUV lithography, and multiple-patterning technology makes routing and placement more difficult. Effective DRC closure requires fundamental modifications to place-and-route technology.

Delivering Competitive PPA

The market seeks ICs with the best performance and the least amount of power usage. Innovative optimization
techniques can achieve time, area, and cost targets while minimizing
power use.

Reducing Time-to-Closure

As wire/via resistance rises, it is becoming increasingly difficult to estimate post-route timing accurately. Pulling detail route visibility early in the flow will help you save iterations, enhance PPA, and shorten time to close.


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