FPGA Design

Is your FPGA design flow prepared for a new class of designs aimed at the most recent complicated FPGAs? Do you have problems with point tools that don’t cooperate? Are you able to accomplish your QoR objectives within the allocated budget? Can your PCB and FPGA teams work together to meet overall system constraints?

Siemens EDA's Complete FPGA Design Flow

Modern SoC design has numerous difficulties, including balancing design complexity, performance/power/area targets, and time-to-market. Design rule complexity and meeting timing make design closure more difficult than ever, necessitating a paradigm shift in place-and-route.

FPGA Design Flow

Trends & Technology

New Class of FPGA Designs & Methodologies

FPGAs are increasingly being employed in rapidly growing industry categories (such as 5G, machine learning, and artificial intelligence) and safety-critical/high-reliability designs. This design category necessitates the application of modern approaches such as HLS or SEE mitigation. It also makes debugging and verifying these huge designs difficult.

Achieving DRC Closure

The extensive usage of mixed-height cells, EUV lithography, and multiple-patterning technology makes routing and placement more difficult. Effective DRC closure requires fundamental modifications to place-and-route technology.

Delivering Competitive PPA

The market seeks ICs with the best performance and the least amount of power usage. Innovative optimization
techniques can achieve time, area, and cost targets while minimizing
power use.

Reducing Time-to-Closure

As wire/via resistance rises, it is becoming increasingly difficult to estimate post-route timing accurately. Pulling detail route visibility early in the flow will help you save iterations, enhance PPA, and shorten time to close.

FPGA Synthesis


Precision Synthesis delivers high-quality output, industry-first features, and seamless interaction with Siemens EDA’s FPGA flow – the industry’s most complete FPGA vendor-independent solution.

HLS & Verification


High-Level C++/SystemC Synthesis with Low-Power estimation/optimization. HLS is more than just “C-to-RTL” because of design validation, code and functional coverage verification, and formalisation.

Equivalence Verification Cover


Static formal verification approaches are used to demonstrate that the design is functionally equivalent to its golden reference. FormalPro allows you to validate designs that would normally take days or weeks in hours or even minutes.

Cost-Effective HDL Simulation


The award-winning Single Kernel Simulator (SKS) technology from ModelSim allows for the transparent integration of VHDL and Verilog in a single design.

Visualizing Complex RTL Design

HDL Designer

HDL Designer combines deep analytic capabilities, rich creative editors, and full project flow management, resulting in increased productivity and a repeatable, predictable design process.

Optimize FPGA/PCB I/OS

FPGA/PCB Co-Design

Remove the boundaries that exist between FPGA and PCB design companies, allowing for more accurate and faster concurrent design processes. Optimize FPGA I/O in relation to the PCB layout.


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