Siemens groundbreaking FPGA synthesis solution offers SEE (Single Event Effects) mitigation for safety-critical and high-reliability designs, supporting multiple vendors. It provides multiple automated & user-controlled mitigation strategies for mil-aero, space, automotive, and medical applications.
For safety-critical and high-reliability applications, Precision Hi-Rel offers industry’s most comprehensive SEE mitigation strategies. And, integration with FormalPro provides assurance that synthesis-based mitigated design is functionally equivalent to the RTL, ensuring DO-254 certification.
TMR is the most popular mitigation strategy used for protection from SEUs/SETs in FPGAs. Precision Hi-Rel provides the widest selection of TMR modes – LTMR, DTMR, GTMR & intelligent Selective TMR (iSTMR), enabling users the trade-off between safety, area, and performance. Inserting TMR at the synthesis level provides greater user control and superior QoR.
Precision Hi-Rel offers two enhanced safe FSM modes:
- SEU Detect – detects invalid transition/state and recovers to a known state
- SEU Tolerant – absorbs an SEU and continues operation without interruption
With seamless integration in the synthesis flow and full user-control, it allows designers to implement these FSM optimizations globally or at a modular level.
FormalPro and Precision Hi-Rel is the industry’s only integration that proves functional equivalence between RTL and the mitigated FPGA design. An FVI setup file, containing synthesis optimization and mitigation information, is auto-generated by Precision, enabling a reliable push-button RTL to gate netlist to mitigated gate netlist equivalence checking.