Today, the typical SoC contains more than 100 IP blocks. These gadgets are strong, but there is a drawback: because of their complexity, it is almost difficult to grasp how they function in any situation. For silicon architects, debug engineers, the SoC bring-up team, and software engineers, this presents a challenge.
Debug, for instance, has a lot of attention right now. It requires up to one-third as much design work as a sophisticated heterogeneous SoC does.
By offering a comprehensive, vendor-neutral view of a device’s activity, Tessent Embedded Analytics addresses every one of these issues while operating at wire speed and without being obtrusive. With our technology, we can cut an 18-month development cycle by up to two months, which translates into cost savings of millions of dollars.
We provide complete code visibility together with the breakpoints, triggers, cross-points, and traces that you would anticipate from a sophisticated debugging solution.
Tessent Embedded Analytics supports a wide range of CPU/GPU architectures, including Arm, MIPS, CEVA, and Cadence Tensilica. It may be used independently or as a supplement to vendor-specific debug solutions (for instance, Arm CoreSight).
While UltraDebug supports normal debug ports, it also uses unique technology that enables simultaneous use of a single high-speed chip interface, such as USB, for system communication and debugging. By doing so, it is no longer necessary to have special debug pins on the device, and data may be sent considerably more quickly than with a conventional serial interface like JTAG.
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