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On-Demand Webinar

Presenter: Avinash Keshav

HDL Simulation Using Commands & Do Files

Brief Summary of Webinar:

Background:
The verification of designs at the software, hardware and firmware level is one of the most important tasks to assure the correct functionality of a designed application. Simulation-based approaches allow the user to monitor the behavior of his/her circuit when faced with given stimuli. This is also known as functional verification. When the complexity of the designs grows, test benches also become more complex and thus require more time to be developed. For this reason, there is a high interest in the industry to reuse code for test benches and streamlining the verification process.
In this webinar, we shall discuss performing simulation using CLI (Command Line interface)

Tool that will be covered:
Questa Advanced Simulator
The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug and functional coverage capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, SVA, UPF and UVM.

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Who should attend?

  • Project Leads
  • FPGA Design & Verification Engineers

Post the session, participants will be able to:

  • Learn how verification planning enables higher quality FPGAs and speeds up debugging.
  • Learn how to run ModelSim or QuestaSim in command line mode.
  • Explain the Libraries and Design Units.
  • Create a working library, mapping a library.
  • Move, copy and delete library directories.

Presenter - Avinash Keshav

More than seven years of experience in technical support of EDA tools while consulting the clients, understanding their requirements, and suggesting solutions in line with their requirements, explaining the capabilities of our software and demonstrating its usefulness towards their design goal. Knowledge of sales & marketing cycle of research and engineering product and FAE’s role in this cycle for maintaining the product relevance in the departments, which procure the EDA tools.

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