Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But High-Level Synthesis (HLS) can make technology-independent design a breeze. High-Level Synthesis (HLS) extends the traditional design flow, providing a new and powerful approach to hardware design. It is important to understand the fundamentals of HLS and how HLS bridges the gap between the RTL designer and architect, and functional verification and RTL verification.
This webinar will discuss how to migrate from FPGA to ASIC and ASIC to FPGA using HLS to accelerate your design flow. How Catapult from Siemens EDA can be used to develop a high-quality RTL resulting into better power, performance, and area.