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On Demand

Presenter: Avinash Keshav

HW Design Engineers: Explore Ease of Migration from FPGA To ASIC And Vice Versa

Brief Summary of Webinar:

Background:

Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But High-Level Synthesis (HLS) can make technology-independent design a breeze. High-Level Synthesis (HLS) extends the traditional design flow, providing a new and powerful approach to hardware design. It is important to understand the fundamentals of HLS and how HLS bridges the gap between the RTL designer and architect, and functional verification and RTL verification.

This webinar will discuss how to migrate from FPGA to ASIC and ASIC to FPGA using HLS to accelerate your design flow. How Catapult from Siemens EDA can be used to develop a high-quality RTL resulting into better power, performance, and area.

Who Should Attend?

  • RTL Designer
  • Architect Designer
  • Verification Engineer

Post the session, the participants will be able to:

  • Learn Fabrics of FPGA and ASIC
  • Learn Intellectual Property usage and its limitations
  • Learn Advantage of Designing at a higher level

ON-DEMAND


Presenter - Avinash Keshav

More than seven years of experience in technical support of EDA tools while consulting the clients, understanding their requirements, and suggesting solutions in line with their requirements, explaining the capabilities of our software and demonstrating its usefulness towards their design goal. Knowledge of sales & marketing cycle of research and engineering product and FAE’s role in this cycle for maintaining the product relevance in the departments, which procure the EDA tools.

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