High-Level Synthesis (HLS) extends the traditional design flow, providing a new and powerful approach to hardware design. It is important to understand the fundamentals of HLS and how HLS bridges the gap between the RTL designer and architect, and functional verification and RTL verification. This webinar will provide an introduction to HLS. How Catapult from Siemens EDA can be used to develop a high-quality RTL resulting into better power, performance and area.
Who Should Attend?
- RTL Designer
- Architect Designer
- Verification Engineer
Post the session, the participants will be able to:
- Learn the HLS Design Flow compared to the traditional design flow.
- Know what does the use of HLS provides?
- Learn the fundamentals of HLS:
- Know to model for HLS
- Learn HLS transformations / optimizations
More than seven years of experience in technical support of EDA tools while consulting the clients, understanding their requirements, and suggesting solutions in line with their requirements, explaining the capabilities of our software and demonstrating its usefulness towards their design goal. Knowledge of sales & marketing cycle of research and engineering product and FAE’s role in this cycle for maintaining the product relevance in the departments, which procure the EDA tools.