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On-Demand Webinar

Presenter: Avinash Keshav

HW Design Engineers: How To Port Vivado HLS Designs to Catapult HLS Platform

Brief Summary of Webinar:

Background:

High-Level Synthesis (HLS) offers significant benefits when developing algorithms and intellectual property (IP) blocks for implementation in digital logic solutions such as Field Programmable Gate Arrays (FPGA) and Application-Specific Integrated Circuits (ASICs). Many FPGA vendors offer HLS tools and using those increases flexibility and productivity over traditional hardware description language (HDL) flows. But employing FPGA vendor-specific tools can limit the portability of the design outside of their ecosystem. To regain the flexibility of targeting a design to another technology requires porting the design from the vendor’s HLS environment into an HLS environment that supports any ASIC or FPGA technology.

Who Should Attend?

  • Designers who are interested in creating a portable solution of ASIC implementation.
  • Engineering Managers who want to know how to leverage existing code bases in new technologies.
  • HLS/RTL designers who are interested in learning about Catapult HLS

Post the session, the participants will be able to:

  • Learn how to port an existing HLS design developed within the Vivado® HLS environment into Catapult® HLS Platform.
  • Learn the differences in libraries and data structures
  • Learn how to port optimizations from Vivado to Catapult

ON-DEMAND


Presenter - Avinash Keshav

More than seven years of experience in technical support of EDA tools while consulting the clients, understanding their requirements, and suggesting solutions in line with their requirements, explaining the capabilities of our software and demonstrating its usefulness towards their design goal. Knowledge of sales & marketing cycle of research and engineering product and FAE’s role in this cycle for maintaining the product relevance in the departments, which procure the EDA tools.

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