Background:
High-Level Synthesis (HLS) offers significant benefits when developing algorithms and intellectual property (IP) blocks for implementation in digital logic solutions such as Field Programmable Gate Arrays (FPGA) and Application-Specific Integrated Circuits (ASICs). Many FPGA vendors offer HLS tools and using those increases flexibility and productivity over traditional hardware description language (HDL) flows. But employing FPGA vendor-specific tools can limit the portability of the design outside of their ecosystem. To regain the flexibility of targeting a design to another technology requires porting the design from the vendor’s HLS environment into an HLS environment that supports any ASIC or FPGA technology.
