On-Demand Webinar

Presenter: Avinash Keshev

HW Designers: Learn What HDL Based Environment Has to Offer for Today’s Most Complex FPGAs & ASICs Design

Brief Summary of Webinar:


Any typical ASIC project includes prototyping the ASIC functionality on an FPGA before handing the design off to the ASIC vendor, which must routinely be completed within a short duration of time. For this the design team needs to accelerate the implementation, debug, documentation, and management of their multimillion gate ASIC designs.

HDL designers working on ASIC/FPGA systems-on-chip (SoC) now have the industry’s most flexible and easy-to-use tool set for design entry, management, and visualization, whether using individual point tools or a complete design flow. This webinar will discuss how HDL Designer from Siemens EDA offers an HDL based environment helps for Today’s most complex FPGAs & ASICs design.

Who Should Attend?

  • RTL Designer
  • Project Manager
  • Architect Designer
  • Verification Engineer


Post the session, the participants will be able to:

  • Learn a structured FPGA/ASIC design flow
  • Deliver a flexible environment for upstream and downstream tools and processes
  • Reduce design creation time through automation


Presenter - Avinash Keshev

More than seven years of experience in technical support of EDA tools while consulting the clients, understanding their requirements, and suggesting solutions in line with their requirements, explaining the capabilities of our software and demonstrating its usefulness towards their design goal. Knowledge of sales & marketing cycle of research and engineering product and FAE’s role in this cycle for maintaining the product relevance in the departments, which procure the EDA tools.

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