With the growing size & complexity, the management of FPGA verification has become a challenging task. Your company can have better predictability and more effective FPGA development through Verification planning and functional coverage. It gives leads and managers the tools they need to maintain perspective on projects. The target is to increase the quality of the design, identify problem areas early, and ensure better schedule predictability by using concrete metrics to track progress.
This session explores how to ensure that debug and verification is done in the most effective place.
Tool that will be covered:
The Questa® Verification Solution transforms verification, dramatically increasing verification productivity and managing resources more efficiently built on several powerful technologies and tightly integrated with Veloce® emulation Questa answers the challenges of increasingly complex SoCs.
- Integrates multiple point tools into flexible, open flows that integrate a broad arsenal of verification solutions.
- Decomposes the problem and employs the best solution, such as CDC verification, formal verification, or mixed-signal simulation, to resolve it.
- Delivers high performance/capacity debug tightly integrated with the Visualizer Debug Environment.
- Increases your ability to build a verification plan and collect metrics to track its progress, allocate and manage resources efficiently, and identify trends as the project progresses against schedule.