This paper tackles the critical signal integrity concerns encountered when designing, simulating, and analyzing DDR buses. The first section describes DDR bus design challenges that can be particularly problematic, even intimidating, to designers. Subsequent sections describe how simulation and analysis speed up the design of a functioning DDR system to reduce PCB spins and shorten the time to release and market.
Tool that will be covered:
HyperLynx DDRX : HyperLynx® DDRx provides powerful integrated signal integrity, crosstalk, and timing analysis that significantly reduces design and debug cycles for PCBs with DDRx memory. Extensive pre-layout, what-if simulations are used to define PCB layout and routing constraints that are driven into the PCB layout flow. Automated post-route simulations extract ‘as-routed’ circuit topologies from PCB databases to perform comprehensive full-interface analysis, validating all signals, groups, and timing relationships at a detailed level before the PCB is sent to manufacturing.
Who Should Attend?
- SI Engineers
- PCB Designers
- Project Managers
Post the session, the participants will be able to:
- Understand DDRx bus validation involves the analysis of several timing and voltage measurements.
- Learn Interfaces have complex signal quality and timing requirements.
- Know Different levels of modeling accuracy, allowing users to trade off accuracy vs. speed
Gowrav has total of 10+ years of expertise handling PCB for High Power & High Voltage designs and High-Speed Design. Involved in layout design for applications in the area of Power Electronics, Custom Power Supplies, Analog Circuits, Digital Power, Solar and Renewable Energy, High-Speed Design differential pair min/max length matching – like DDR 2/3 boards. handling the portfolio of Mentor PCB software’s Pre-Sales & post Sales.