Background:
As SoC designs are evolving and growing in complexity to match the capabilities of today’s ASIC and FPGA technologies, so too are the test benches and verification flows built around those designs. There are new criteria driving evolution in complexity – such as concurrent DUT stimulus, multi-level reuse of components and sequences, portability from the simulator to emulator enabled by today’s emulator architecture, and increasingly common is that design/verification teams are split across locations and geographies, collaborating on mega-gate designs. This kind of development requires speed – speed of execution, speed of turnaround, and ultimately speed of the tools in the flow. What is needed is a simulation build/regression flow where the tools are optimized for maximum speed, and minimum turnaround time.
In this session, you will learn best practice in verification flows in the industry today, and how to implement the optimal flow to speed your SoC design verification cycle.
On-Demand Webinar
Presenter: Avinash Keshav
Verification Engineers: Break The Speed Limit On SOC Verification With Questa
Who Should Attend?
- Project Leads
- FPGA/ASIC Design & Verification Engineers
Post the session, the participants will be able to:
- Learn Block-, Subsystem-, and SoC-level verification flows in common use in the industry today
- Learn how the best practice in the design of the verification flow leads to improved productivity
- Learn how Questa Simulator is providing the highest performance across the flow
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Presenter - Avinash Keshav
More than seven years of experience in technical support of EDA tools while consulting the clients, understanding their requirements, and suggesting solutions in line with their requirements, explaining the capabilities of our software and demonstrating its usefulness towards their design goal. Knowledge of sales & marketing cycle of research and engineering product and FAE’s role in this cycle for maintaining the product relevance in the departments, which procure the EDA tools.